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1 ? fn6337.2 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2007, 2008. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl28148, isl28248, ISL28448 4.5mhz, single dual and quad precision rail-to-rail input-output (rrio) op amps with very low input bias current the isl28148, isl28248 and ISL28448 are 4.5mhz low-power single, dual and quad operational amplifiers. the parts are optimized for single supply operation from 2.4v to 5.5v, allowing operation from one lithium cell or two ni-cd batteries. the single, dual and quad feature an input range enhancement circuit (i rec) which enables them to maintain cmrr performance for input voltages greater than the positive supply. the input signal is capable of swinging 0.25v above the positive supply and to 100mv below the negative supply with only a sl ight degradation of the cmrr performance. the output operation is rail-to-rail. the parts draw minimal supply current (900a per amplifier) while meeting excellent dc accuracy, ac performance, noise and output drive specific ations. the isl28148 features an enable pin that can be used to turn the device off and reduce the supply current to a maximum of 16a. operation is guaranteed over -40c to +125c temperature range. features ? 4.5mhz gain bandwidth product ? 900a supply current (per amplifier) ? 1.8mv maximum offset voltage ? 1pa typical input bias current ? down to 2.4v single supply operation ? rail-to-rail input and output ? enable pin (isl28148 sot-23 package only) ? -40c to +125c operation ? pb-free (rohs compliant) applications ? low-end audio ? 4ma to 20ma current loops ? medical devices ? sensor amplifiers ? adc buffers ? dac output amplifiers ordering information part number part marking package (pb-free) pkg. dwg. # isl28148fhz-t7* (note 1) gabt 6 ld sot-23 (tape and reel) mdp0038 isl28148fhz-t7a* (note 1) gabt 6 ld sot-23 (tape and reel) mdp0038 coming soon, isl28148fiz-t7 (note 2) 178z 6 ld wlcsp (1.5mmx1.0mm) w3x2.6c coming soon, isl28248fbz (note 1) 28248bz 8 ld soic mdp0027 coming soon, isl28248fbz-t7* (note 1) 28248bz 8 ld soic (tape and reel) mdp0027 coming soon, isl28248fuz (note 1) 8248z 8 ld msop mdp0043 coming soon, isl28248fuz-t7* (note 1) 8248z 8 ld msop (tape and reel) mdp0043 coming soon, ISL28448fvz (note 1) mxz 14 ld tssop mdp0044 coming soon, ISL28448fvz-t7* (note 1) mxz 14 ld tssop (tape and reel) mdp0044 *please refer to tb347 for detai ls on reel specifications. notes: 1. these intersil pb-free plastic packaged pr oducts employ special pb-free material se ts; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-free re quirements of ipc/jedec j std-020. 2. these intersil pb-free wlcsp and bga packaged products products em ploy special pb-free material sets; molding compounds/die a ttach materials and snagcu - e1 solder ball terminals, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free wlcsp and bga packaged products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 13, 2008
2 fn6337.2 march 13, 2008 pinouts isl28148 (6 ld sot-23) top view isl28148 (6 ld wlcsp) top view isl28248 (8 ld soic) top view isl28248 (8 ld msop) top view ISL28448 (14 ld tssop) top view 1 2 3 6 4 5 +- out v- in+ v+ en in- 2 1 a b c out v - in + nc v + in - 1 2 3 4 8 7 6 5 out_a in-_a in+_a v+ out_b in-_b v- in+_b + - +- 1 2 3 4 8 7 6 5 out_a in-_a in+_a v+ out_b in-_b v- in+_b + - +- out_a in-_a in+_a v+ in+_b in-_b out_b out_d in-_d in+_d v- in+_c in-_c out_c 1 2 3 4 5 6 7 14 13 12 11 10 9 8 + - +- + - +- isl28148, isl28248, ISL28448
3 fn6337.2 march 13, 2008 absolute maxi mum ratings (t a = +25c) thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75v supply turn on voltage slew rate . . . . . . . . . . . . . . . . . . . . . 1v/ s differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v- - 0.5v to v+ + 0.5v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v thermal resistance (typical, note 3) ja (c/w) 6 ld sot-23 package . . . . . . . . . . . . . . . . . . . . . . . 230 6 ld wlcsp package . . . . . . . . . . . . . . . . . . . . . . . 130 8 ld so package . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8 ld msop package . . . . . . . . . . . . . . . . . . . . . . . . 175 14 ld tssop package . . . . . . . . . . . . . . . . . . . . . . 115 ambient operating temperature range . . . . . . . . .-40c to +125c storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temperature . . . . . . . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v+ = 5v, v- = 0v,v cm = 2.5v, r l = open , t a = +25c unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . parameter description conditions min (note 4) typ max (note 4) unit v os input offset voltage - 1.8 -2 0 1.8 2 mv csp package - 1.0 -1.2 -0.1 1.0 1.2 input offset voltage vs temperature 0.03 v/c i os input offset current t a = -40c to +85c -35 -80 535 80 pa i b input bias current t a = -40c to +85c -30 -80 130 80 pa csp package -40 -90 130 80 cmir common-mode voltage range guaranteed by cmrr 05 v cmrr common-mode rejection ratio v cm = 0v to 5v 75 70 98 db psrr power supply rejection ratio v + = 2.4v to 5.5v 80 75 98 db a vol large signal voltage gain v o = 0.5v to 4.5v, r l = 100k to v cm 200 150 580 v/mv v o = 0.5v to 4.5v, r l = 1k to v cm 50 v/mv v out maximum output voltage swing output low, r l = 100k to v cm 36 8 mv output low, r l = 1k to v cm 50 70 110 mv output high, r l = 100k to v cm 4.994 4.99 4.998 v output high, r l = 1k to v cm 4.93 4.89 4.95 v v os t --------------- - isl28148, isl28248, ISL28448
4 fn6337.2 march 13, 2008 i s,on quiescent supply current, enabled 0.7 0.4 0.9 1.1 1.4 ma i s,off quiescent supply current, disabl ed isl28148 sot-23 package only 10 14 16 a i o + short-circuit output source current r l = 10 to v cm 48 45 75 ma i o - short-circuit output sink current r l = 10 to v cm 50 45 68 ma v supply supply operating range v+ to v- 2.4 5.5 v v enh en pin high level isl28148 sot-23 package only 2 v v enl en pin low level isl28148 sot-23 package only 0.8 v i enh en pin input high current v en = v+,isl28148 sot-23 package only 11.5 1.6 a i enl en pin input low current v en = v-, isl28148 sot-23 package only 12 25 30 na ac specifications gbw gain bandwidth product a v = 100, r f = 100k , r g = 1k , r l = 10k to v cm 4.5 mhz unity gain bandwidth -3db bandwidth a v =1, r f = 0 , v out = 10mv p-p , r l = 10k to v cm 13 mhz e n input noise voltage peak-to-peak f = 0.1hz to 10hz 2 v pp input noise voltage density f o = 1khz 28 nv / hz i n input noise current density f o = 1khz 0.016 pa/ hz cmrr @ 60hz input common mode rejection ratio v cm = 1v p-p , r l = 10k to v cm 85 db psrr- @ 120hz power supply rejection ratio (v - )v + , v - = 1.2v and 2.5v, v source = 1v p-p , r l = 10k to v cm -82 db psrr+ @ 120hz power supply rejection ratio (v + )v + , v - = 1.2v and 2.5v v source = 1v p-p , r l = 10k to v cm -100 db transient response sr slew rate 4v/s t r , t f , large signal rise time, 10% to 90%, v out a v = +2, v out = 3v p-p , r g = r f = 10k r l = 10k to v cm 530 ns fall time, 90% to 10%, v out a v = +2, v out = 3v p-p , r g = r f = 10k r l = 10k to v cm 530 ns t r , t f , small signal rise time, 10% to 90%, v out a v = +2, v out = 10mv p-p , r g = r f = r l = 10k to v cm 50 ns fall time, 90% to 10%, v out a v = +2, v out = 10mv p-p , r g = r f = r l = 10k to v cm 50 ns t en enable to output turn-on delay time, 10% en to 10% v out , (isl28148) en = 5v to 0v, a v = +2, r g = r f = r l = 1 k to v cm 5s enable to output turn-off delay time, 10% en to 10% v out , (isl28148) v en = 0v to 5v, a v = +2, r g = r f = r l = 1 k to v cm 0.2 s note: 4. parts are 100% tested at +25c. temperature limits established by characterizati on and are not production tested. electrical specifications v+ = 5v, v- = 0v,v cm = 2.5v, r l = open , t a = +25c unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +125c. temperature data established by characterization . (continued) parameter description conditions min (note 4) typ max (note 4) unit isl28148, isl28248, ISL28448
5 fn6337.2 march 13, 2008 typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open figure 1. gain vs frequency vs feedback resistor values r f /r g figure 2. gain vs frequency vs v out, r l = 1k figure 3. gain vs frequency vs v out , r l = 10k figure 4. gain vs frequency vs v out , r l = 100k figure 5. gain vs frequency vs r l figure 6. frequency resp onse vs closed loop gain -15 -10 -5 0 5 10 15 100 1k 10k 100k 1m 10m 100m frequency (hz) v + = 5v r l = 1k a v = +2 v out = 10mv p-p c l = 16.3pf r f = r g = 100k r f = r g = 1k r f = r g = 10k normalized gain (db) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 1k 10k 100k 1m 10m 100m frequency (hz) v out = 100mv v + = 5v r l = 1k a v = +1 c l = 16.3pf v out = 50mv v out = 10mv v out = 1v normalized gain (db) -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 1k 10k 100k 1m 10m 100m frequency (hz) v + = 5v r l = 10k a v = +1 c l = 16.3pf normalized gain (db) v out = 100mv v out = 50mv v out = 10mv v out = 1v -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 normalized gain (db) 1k 10k 100k 1m 10m 100m frequency (hz) v + = 5v r l = 100k a v = +1 c l = 16.3pf v out = 100mv v out = 50mv v out = 10mv v out = 1v -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 normalized gain (db) 1k 10k 100k 1m 10m 100m frequency (hz) v + = 5v v out = 10mv p-p a v = +1 c l = 16.3pf r l = 100k r l = 10k r l = 1k -10 0 10 20 30 40 50 60 70 gain (db) 1k 10k 100k 1m 10m 100m frequency (hz) 100 a v = 1001 a v = 101 a v = 10 a v = 1 v + = 5v v out = 10mv p-p c l = 16.3pf r l = 10k a v = 1, r g = inf, r f = 0 a v = 10, r g = 1k, r f = 9.09k a v = 101, r g = 1k, r f = 100k a v = 1001, r g = 1k, r f = 1m isl28148, isl28248, ISL28448
6 fn6337.2 march 13, 2008 figure 7. gain vs frequency vs supply voltage figure 8. gain vs frequency vs c l figure 9. cmrr vs frequency; v + = 2.4v and 5v figure 10. psrr vs frequency, v + , v - = 1.2v figure 11. psrr vs frequency v + , v - = 2.5v figure 12. input voltage noise density vs frequency typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) 10k 100k 1m 10m 100m frequency (hz) v + = 2.4v v + = 5v -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 normalized gain (db) r l = 10k a v = +1 v out = 10mv p-p c l = 16.3pf -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 10k 100k 1m 10m 100m frequency (hz) normalized gain (db) c l = 51.7pf c l = 37.7pf c l = 26.7pf c l = 16.7pf c l = 4.7pf v + = 5v r l = 1k a v = +1 v out = 10mv p-p c l = 43.7pf -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1k 10k 100k 1m 10m frequency (hz) v + = 2.4v, 5v r l = 1k a v = +1 v cm = 1v p-p c l = 16.3pf cmrr (db) -120 -100 -80 -60 -40 -20 0 20 psrr (db) 100 1k 10k 100k 1m 10m frequency (hz) v + , v - = 1.2v r l = 1k a v = +1 v cm = 1v p-p c l = 16.3pf psrr- psrr+ -120 -100 -80 -60 -40 -20 0 20 psrr (db) 100 1k 10k 100k 1m 10m frequency (hz) v + , v - = 2.5v r l = 1k a v = +1 v cm = 1v p-p c l = 16.3pf psrr- psrr+ frequency (hz) 10 100 1000 1 10 100 1k 10k 100k input voltage noise (nv/ hz) v + = 5v a v = +2 r f =1k r g =1k isl28148, isl28248, ISL28448
7 fn6337.2 march 13, 2008 figure 13. input current noise density vs freque ncy figure 14. input voltage noise 0.1hz to 10hz figure 15. large signal step response figure 16. small signal step response figure 17. isl28148 enable to output response typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) frequency (hz) 0.01 0.1 1 10 100 1k 10k 100k input current noise (pa/hz) v + = 5v a v = +2 r f =1k r g =1k -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 012345678910 time (s) input noise (v) v + = 5v r l = 10k r g = 10 a v = 10k c l = 16.3pf r f = 100k -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 0123456789 time (s) v + , v - = 2.5v r l = 1k r g = r f = 10k a v = 2 c l = 16.3pf v out = 3v p-p large signal (v) 10 0.010 0.015 0.020 0.025 012345678910 time (s) v + , v - = 2.5v r l = 1k r g = r f = 10k a v = 2 c l = 16.3pf v out = 10mv p-p small signal (v) -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 102030405060708090100 time (s) -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 v + = 5v r g = r f = 10k a v = +2 v out = 1v p-p c l = 16.3pf v en v out r l = 10k v enable (v) output (v) isl28148, isl28248, ISL28448
8 fn6337.2 march 13, 2008 figure 18. input offset voltage vs common mode input voltage figure 19. input bias current vs common mode input voltage figure 20. supply current enabled vs temperature v + , v - = 2.5v figure 21. supply current disabled vs temperature v + , v - = 2.5v figure 22. v os vs temperature v in = 0v, v + , v - = 2.75v figure 23. v os vs temperature v in = 0v, v + , v - = 2.5v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) -800 -600 -400 -200 0 200 400 600 800 -10123456 v cm (v) v + = 5v r l = open a v = +1k r f = 100k, r g = 100 v os (v) -100 -80 -60 -40 -20 0 20 40 60 80 100 -10123456 v cm (v) i bias (pa) v + = 5v r l = open a v = +1k r f = 100k, r g = 100 0.6 0.7 0.8 0.9 1.0 1.1 1.2 -40-200 20406080100120 temperature (c) current (a) max median min 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 -40-200 20406080100120 temperature (c) current (a) max median min -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 v os (mv) median min max -40-200 20406080100120 temperature (c) median min max -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 v os (mv) -40-200 20406080100120 temperature (c) isl28148, isl28248, ISL28448
9 fn6337.2 march 13, 2008 figure 24. v os vs temperature v in = 0v, v + , v - = 1.2v figure 25. csp package v os vs temperature v in = 0v, v + , v - = 2.75v figure 26. csp package v os vs temperature v in = 0v, v + , v - = 2.5v figure 27. csp package v os vs temperature v in = 0v, v + , v - = 1.2v figure 28. i bias - vs temperature v + , v - = 2.5v figure 29. i bias - vs temperature v + , v - = 1.2v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) median min max -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 v os (mv) -40 -20 0 20 40 60 80 100 120 temperature (c) -1.5 -1 -0.5 0 0.5 1 1.5 -40 -20 0 20 40 60 80 100 120 temperature (c) median min max v os (mv) -1.5 -1 -0.5 0 0.5 1 1.5 -40-200 20406080100 120 temperature (c) v os (mv) median min max -1.5 -1 -0.5 0 0.5 1 1.5 -40 -20 0 20 40 60 80 100 120 temperature (c) v os (mv) median min max -50 0 50 100 150 200 250 300 i bias - (pa) -40-200 20406080100120 temperature (c) max median min -50 0 50 100 150 200 250 i bias - (pa) max median min -40-200 20406080100120 temperature (c) isl28148, isl28248, ISL28448
10 fn6337.2 march 13, 2008 figure 30. csp package i bias - vs temperature v + , v - = 2.5v figure 31. csp package i bias - vs temperature v + , v - = 1.2v figure 32. i os vs temperature v + , v - = 2.5v figure 33. i os vs temperature v + , v - = 1.2v figure 34. a vol vs temperature r l = 100k, v + , v - = 2.5v, v o = -2v to +2v figure 35. a vol vs temperature r l = 1k, v + , v - = 2.5v, v o = -2v to +2v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) -50 0 50 100 150 200 250 300 350 400 -40 -20 0 20 40 60 80 100 120 temperature (c) ibias -(pa) max median min -50 0 50 100 150 200 250 300 350 -40-200 20406080100120 temperature (c) ibias - (pa) max median min -70 -60 -50 -40 -30 -20 -10 0 10 i os (pa) -40 -20 0 20 40 60 80 100 120 temperature (c) max median min -60 -50 -40 -30 -20 -10 0 10 20 i os (pa) -40 -20 0 20 40 60 80 100 120 temperature (c) max median min 150 350 550 750 950 1150 1350 1550 1750 a vol (v/mv) max median min -40-200 20406080100120 temperature (c) 20 30 40 50 60 70 80 max min median a vol (v/mv) -40 -20 0 20 40 60 80 100 120 temperature (c) isl28148, isl28248, ISL28448
11 fn6337.2 march 13, 2008 figure 36. cmrr vs temperature v cm = -2.5v to +2.5v, v +, v - = 2.5v figure 37. psrr vs temperature v +, v - = 1.2v to 2.75v figure 38. v out high vs temperature r l = 1k, v + , v - = 2.5v figure 39. v out high vs temperature r l = 100k, v + , v - = 2.5v figure 40. v out low vs temperature r l = 1k, v + , v - = 2.5v figure 41. v out low vs temperature r l = 100k, v + , v - = 2.5v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) -40-200 20406080100120 temperature (c) 70 80 90 100 110 120 130 140 cmrr (db) max median min 70 80 90 100 110 120 130 140 psrr (db) max median min -40 -20 0 20 40 60 80 100 120 temperature (c) 4.940 4.945 4.950 4.955 4.960 4.965 4.970 v out (v) max median min -40-200 20406080100120 temperature (c) 4.9982 4.9984 4.9986 4.9988 4.9990 4.9992 4.9994 v out (v) max median min -40-200 20406080100120 temperature (c) 40 45 50 55 60 65 70 75 v out (mv) max median min -40-200 20406080100120 temperature (c) 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 v out (mv) max median min -40 -20 0 20 40 60 80 100 120 temperature (c) isl28148, isl28248, ISL28448
12 fn6337.2 march 13, 2008 figure 42. + output short circuit current vs temperature v in = -2.55v, r l = 10, v + , v - = 2.5v figure 43. - output short circuit current vs temperature v in = -2.55v, r l = 10, v + , v - = 2.5v typical performance curves v+ = 5v, v- = 0v, v cm = 2.5v, r l = open (continued) 60 65 70 75 80 85 90 95 + output short circuit current (ma) median min max -40 -20 0 20 40 60 80 100 120 temperature (c) -85 -80 -75 -70 -65 -60 -55 -50 median min max - output short circuit current (ma) -40 -20 0 20 40 60 80 100 120 temperature (c) median min max pin descriptions isl28148 (6 ld sot-23) isl28148 6 ld wlcsp isl28248 (8 ld so) (8 ld msop) ISL28448 (14 ld tssop) pin name function equivalent circuit nc not connected 4c1 2 (a) 6 (b) 2 (a) 6 (b) 9 (c) 13 (d) in- in-_a in-_b in-_c in-_d inverting input circuit 1 3c2 3 (a) 5 (b) 3 (a) 5 (b) 10 (c) 12 (d) in+ in+_a in+_b in+_c in+_d non-inverting input (see circuit 1) 2 b2 4 11 v- negative supply circuit 2 1a2 1 (a) 7 (b) 1 (a) 7 (b) 8 (c) 14 (d) out out_a out_b out_c out_d output circuit 3 6 b1 8 4 v+ positive supply (see circuit 2) in- v+ v- in+ v+ v- capacitively coupled esd clamp v + v- out isl28148, isl28248, ISL28448
13 fn6337.2 march 13, 2008 applications information introduction the isl28148, isl28248 and ISL28448 are single, dual and quad channel cmos rail-to-ra il input, output (rrio) micropower precision operational amplifiers. the parts are designed to operate from single supply (2.4v to 5.5v) or dual supply (1.2v to 2.75v). the parts have an input common mode range that extends 0.25v above the positive rail and 100mv below the negative suppl y rail. the output operation can swing within about 3mv of the supply rails with a 100k load. rail-to-rail input many rail-to-rail input stages us e two differential input pairs, a long-tail pnp (or pfet) and an npn (or nfet). severe penalties have to be paid for this circuit topology. as the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. the parts achieve input rail-to-rail operation without sacrificing important precision specifications and degrading distortion performance. the devices? input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. the input bias current vs the common-mode voltage range gives us an undistorted behavior from typically 100mv below the negative rail and 0.25v higher than the v+ rail. rail-to-rail output a pair of complementary mos devices are used to achieve the rail-to-rail output swing. the nmos sinks current to swing the output in the negative direction. the pmos sources current to swing the out put in the positive direction. the devices? with a 100k load will swing to within 3mv of the positive supply rail and within 3mv of the negative supply rail. results of over-driving the output caution should be used when over-driving the output for long periods of time. over-driving the output can occur in two ways: 1. the input voltage times the gain of the amplifier exceeds the supply voltage by a large value or 2. the output current required is higher than the output stage can deliver. these conditions can result in a shift in the input offset voltage (v os ) as much as 1v/hr. of exposure under these condition. in+ and in- input protection all input terminals have internal esd protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. they also contain back-to-back diodes across the input terminals (?pin descriptions? table - circuit 1 on page 12 ) . for applications where the input differential vo ltage is expected to exceed 0.5v, an external series resistor must be used to ensure the input currents never exceed 5ma (figure 44). enable/disable feature the isl28148 offers an en pin that disables the device when pulled up to at least 2.0v. in the disabled state (output in a high impedance state), the part consumes typically 10a at room temperature. by di sabling the part, multiple isl28148 parts can be connected together as a mux. in this configuration, the outputs are tied together in parallel and a channel can be selected by the en pin. the loading effects of the feedback resistors of the disabled amplifier must be considered when multiple amp lifier outputs are connected together. note that feed through from the in+ to in- pins occurs on any mux amp disabled channel where the input differential voltage exceeds 0.5v (e.g., active channel v out = 1v, while disabled channel v in = gnd), so the mux 5- en chip enable circuit 4 a1 nc connect pin to the most negative supply pin descriptions (continued) isl28148 (6 ld sot-23) isl28148 6 ld wlcsp isl28248 (8 ld so) (8 ld msop) ISL28448 (14 ld tssop) pin name function equivalent circuit v + v- en figure 44. input current limiting - + r in r l v in v out isl28148, isl28248, ISL28448
14 fn6337.2 march 13, 2008 implementation is best suited for small signal applications. if large signals are required, use series in+ resistors, or large value r f , to keep the feed through current low enough to minimize the impact on the acti ve channel. see ?limitations of the differential input protection? on page 14 for more details.the en pin also has an internal pull-down. if left open, the en pin will pull to the negative rail and the device will be enabled by default. when not used, the en pin should either be left floating or connected directly to the v- pin. limitations of the differ ential input protection if the input differential voltage is expected to exceed 0.5v, an external current limiting resistor must be used to ensure the input current never exceeds 5ma. for non-inverting unity gain applications the current limiting can be via a series in+ resistor, or via a feedback resistor of appropriate value. for other gain configurations, the series in+ resistor is the best choice, unless the feedback (r f ) and gain setting (r g ) resistors are both sufficiently large to limit the input current to 5ma. large differential input voltages can arise from several sources: ? during open loop (comparator) operation. used this way, the in+ and in- voltages don?t track, so differentials arise. ? when the amplifier is disabled but an input signal is still present. an r l or r g to gnd keeps the in- at gnd, while the varying in+ signal creates a differential voltage. mux amp applications are similar, except that the active channel v out determines the voltage on the in- terminal. ? when the slew rate of the input pulse is considerably faster than the op amp?s slew rate. if the v out can?t keep up with the in+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. to avoid this issue, keep the input slew rate below 4.8v/ s, or use appropriate current limiting resistors. large (>2v) differential input voltages can also cause an increase in disabled i cc . using only one channel if the application does not us e all channels, then the user must configure the unused channel(s) to prevent them from oscillating. the unused channel( s) will oscillate if the input and output pins are floating. th is will result in higher than expected supply currents and possible noise injection into the channel being used. the proper way to prevent this oscillation is to short the out put to the negative input and ground the positive input (as shown in figure 45). proper layout maximizes performance to achieve the maximum performance of the high input impedance and low offset voltage, care should be taken in the circuit board layout. the pc board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. when input leakage current is a concern, the use of guard rings around the amplifier inputs will further reduce leakage currents. figure 46 shows a guard ring example for a unity gain amplifier that uses the low im pedance amplifier output at the same voltage as the high impedance input to eliminate surface leakage. the guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. for further reduction of leakage currents, components can be mounted to the pc board using teflon standoff insulators. . current limiting these devices have no internal current-limiting circuitry. if the output is shorted, it is po ssible to exceed the absolute maximum rating for output current or power dissipation, potentially resulting in the destruction of the device. power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power-supply conditions. it is therefore important to calculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. these paramete rs are related in equation 1: where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated as shown in equation 2: figure 45. preventing oscillations in unused channels - + in v+ figure 46. guard ring example for unity gain amplifier high impedance input t jmax t max ja xpd maxtotal () + = (eq. 1) pd max 2*v s i smax v s ( - v outmax ) v outmax r l ---------------------------- + = (eq. 2) isl28148, isl28248, ISL28448
15 fn6337.2 march 13, 2008 where: ?t max = maximum ambi ent temperature ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = supply voltage (magnitude of v + and v - ) ?i max = maximum supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application ?r l = load resistance isl28148, isl28248, ISL28448
16 fn6337.2 march 13, 2008 isl28148, isl28248, ISL28448 sot-23 package family e1 n a d e 4 3 2 1 e1 0.15 d c 2x 0.20 c 2x e b 0.20 m d c a-b b nx 6 2 3 5 seating plane 0.10 c nx 1 3 c d 0.15 a-b c 2x a2 a1 h c (l1) l 0.25 0 +3 -0 gauge plane a mdp0038 sot-23 package family symbol millimeters tolerance sot23-5 sot23-6 a 1.45 1.45 max a1 0.10 0.10 0.05 a2 1.14 1.14 0.15 b 0.40 0.40 0.05 c 0.14 0.14 0.06 d 2.90 2.90 basic e 2.80 2.80 basic e1 1.60 1.60 basic e 0.95 0.95 basic e1 1.90 1.90 basic l 0.45 0.45 0.10 l1 0.60 0.60 reference n 5 6 reference rev. f 2/07 notes: 1. plastic or metal protrusions of 0.25mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. this dimension is measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994. 5. index area - pin #1 i.d. will be located within the indicated zone (sot23-6 only). 6. sot23-5 version has no center lead (shown as a dashed line).
17 fn6337.2 march 13, 2008 isl28148, isl28248, ISL28448 wafer level chip scale package (wlcsp) pin 1 id a e1 bottom view cb a b d 1 side view a 1 a 2 top view d e sd 2 1 e se b w3x2.6c 3x2 array 6 ball wafer level chip scale package symbol millimeters a 0.51 min, 0.55 max a 1 0.225 0.015 a 2 0.305 0.013 b 0.323 0.025 d 0.955 0.020 d 1 0.50 basic e 1.455 0.020 e 1 1.00 basic e 0.50 basic sd 0.25 basic se 0.00 basic rev. 3 03/08 notes: 1. all dimensions are in millimeters.
18 fn6337.2 march 13, 2008 isl28148, isl28248, ISL28448 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
19 fn6337.2 march 13, 2008 isl28148, isl28248, ISL28448 mini so package family (msop) 1 (n/2) (n/2)+1 n plane seating n leads 0.10 c pin #1 i.d. e1 e b detail x 3 3 gauge plane see detail "x" c a 0.25 a2 a1 l 0.25 c a b d a m b e c 0.08 c a b m h l1 mdp0043 mini so package family symbol millimeters tolerance notes msop8 msop10 a 1.10 1.10 max. - a1 0.10 0.10 0.05 - a2 0.86 0.86 0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 0.05 - d 3.00 3.00 0.10 1, 3 e 4.90 4.90 0.15 - e1 3.00 3.00 0.10 2, 3 e 0.65 0.50 basic - l 0.55 0.55 0.15 - l1 0.95 0.95 basic - n 8 10 reference - rev. d 2/07 notes: 1. plastic or metal protrusions of 0.15mm maximum per side are not included. 2. plastic interlead protrusions of 0.25mm maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m-1994.
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6337.2 march 13, 2008 isl28148, isl28248, ISL28448 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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